FPGA Advances Offer Both Capabilities and Challenges

As FPGAs migrate to roles as “System Chips” they contain ever more valuable defense sensitive data and engineering. Keeping those resources safe and secure raises challenging issues.


Countless articles in COTS Journal and other publications highlight the importance, applications, and the success of Field Programmable Gate Arrays (FPGAs) in defense programs. The FPGAs themselves have changed dramatically in ways that augment this success. Advances include the addition of Digital Signal Processing (DSP) blocks, memory resources, high speed data protocol support, extended temperature range support, hardened processors (SoCs), and security features.

The latest generation of 16nm and 14nm products are expanding these inroads even further. The leading FPGA developers have aggressively developed products on the newest silicon manufacturing technologies. That’s driven by the aggregation of applications they can accommodate on a single FPGA platform. These leading-edge technologies then compete economically with ASICS, ASSPs, and other technologies for the limited volumes of many defense applications. In contrast, new custom ASICs entail exponentially increasing NRE expenses on leading silicon technology nodes that are otherwise amortized across different markets and users with FPGA products.

Attractive FPGA Features

The radar and electronic warfare applications of FPGA DSP blocks have been extensively documented by users and providers of FPGA technology. New features for military applications in recent product offerings include the hardening of single precision floating point operations and design/synthesis tool support for hardened floating point. That allows for higher resolution beam forming and image deconstruction and the ability to exploit the higher resolution analog-to-digital converters available in the market (Figure 1).

Figure 1. Hardened floating point features on FPGAs enable higher resolution beam forming and image deconstruction.

The combination of more sophisticated security architectures, and the promise of domestic fabrication, also ensure that a trusted FPGA product can be provided to the defense market. Some vendors also provide application-focused reference designs and tailored development kits useful for defense and government applications. When combined with DSP-oriented design tools and high level synthesis code support and compilers, FPGAs become attractive for performance reasons but also development time and cost reasons.

Finally, multi-die integration technology from multiple vendors has enabled the capability for mixed circuit technology in a single package. That reduces chip-to-chip latencies while reducing the physical security footprint of the overall solution. All that adds up to solutions with in-package memory, analog-to-digital converters, and other solutions for applications like electronic warfare where processing time requirements and latency sensitivities are critical to performance.

Example FPGA Breakthroughs

One of the primary technologies enabled by high performance and high density FPGAs is classical beam forming and signal processing. Programmable logic is well-suited for customizing digital beam steering and concentration capabilities. That serves the needs of high performance sensors and jammers, and more recently enables wireless communication infrastructures with the advent of the 5G standard.

Another more recent breakthrough is the capability to perform artificial intelligence or machine learning applications on a single chip or small number of chips. Doing that requires either a massive tailored ASIC development or high density FPGA to conduct the wide parallelization of convolutional neural networks or other technology for use in targeting automation and image recognition.

In any of those scenarios, the ‘defense application sensitive’ data is typically an algorithm that is implemented in the software of a commercial FPGA product. However, the breakthrough performance of these defense applications is highly dependent on the component technology and novel multi-die commercial products, and sometimes on the design and optimization tools used and intellectual property blocks leveraged. That means the defense application itself, as well as its implementation on commercial technology both need protecting.

Defense Sensitive Technologies

For years, many of the more sophisticated defense sensor and processing technologies have taken advantage of the raw computing power of workhorses like FPGAs, GPUs, embedded processors, and high speed memories. As these heterogeneous computing applications are moved into smaller form factors, multi-die chips, and more tightly coupled configurations the interest from the defense sector has only grown. The enabling technologies, in some instances, become the forces of ‘silicon convergence’ and highly capable systems-on-chip. As a consequence, defense sensitive information lies not only in the algorithms themselves but also in the engineering knowledge of how those algorithms are implemented across multiple electronic components (Figure 2). This ‘know how’ is a combined effort between defense developers and commercial chip vendors.

Figure 2. Defense sensitive information resides not only in the algorithms themselves but also in the engineering knowledge of how those algorithms are implemented on an FPGA.

Systems integration, and getting multiple small components to work together in a low latency environment, is an enormously difficult technical task—arguably the most important activity in defense development today. It often entails technical support from one or more component providers. And even more support is needed when there are multiple electronic components from a single vendor in a design. FPGAs and SoCs are by their nature complicated devices, and defense customers develop very complex systems using these technologies. Abstracting the sensitive defense application from a customer support engagement likewise enters a new realm of complexity.

Protecting Sensitive Technologies

Companies like Intel as commercial providers of semiconductor technology to the Department of Defense need to recognize these new complexities, and be proactive in protecting the defense sensitive information of customers. While there will always be tailored processes for each defense engagement as required by the U.S. Government, it is important that a common set of data handling procedures be identified for classifying, marking, and handling defense customer information—both for data protection and data audit purposes (Figure 3).

Figure 3. Sensitive information handling policy and procedures make up the first level of an overall information protection strategy.

It is likewise important that we handle and separate information in such a way that commercial technologies like FPGAs remain commercial and dual-use, both for economic viability as well as the ability to take advantage of all breakthroughs in the commercial semiconductor industry. It has been well over 20 years now that the Department of Defense recognized and mandated the use of commercial technology in defense systems, and this responsibility includes making sure that these technologies remain in the commercial marketplace.

The types of data involved in supporting a customer engagement can include a variety of things. This can include specifics of customer requirements, including numbers of channels and data rates that may reveal radio frequency technologies elsewhere in the system. This can include customer schematics and board layouts, typically attended by an FPGA or semiconductor applications engineer to ensure correct power tree design and pin assignments. It can also include specific debug support requests in a bug tracking system that can reveal operations aspects of a defense system. And of course, this type of data can also include whole or partial source code of a design provided for benchmarking and debug purposes.

Information Handling Procedures

In order to responsibly supply the defense electronics market, it is the responsibility of commercial technology providers to offer strong data handling procedures for the protection of defense technology. This includes, but is not limited to, supplier-user agreements on document marking and classification when design information is exchanged or reviewed. Clear audit trails should apply not only to exchanged information, but also to the service request processes and what consultation occurred during these service requests. Finally, well-defined checklists should be used when deciding exactly what defense customer design information makes its way into the data networks of commercial providers, and when such information should not be transferred at all. Throughout, human resources and program management tracking should ensure that only US citizens or persons are utilized when conducting support activities of defense systems.

Providers of defense systems need to operate in safe and controlled environments in order to protect leading edge military capabilities. And high performance silicon providers need to operate in fast-paced, agile, and high communication environments capable of maintaining a competitive edge. Information needs to be treated very differently in these two environments, and so the transfer of information between these environments requires regulation and control. At the same time, creating extremely high performance multi-die solutions and design software requires more transfer of application information than ever before.

At the end of the day, all these additional data handling procedures should have the goal in mind of making commercial technologies acceptable, economical, and most importantly, safe to use in defense system designs. Technology trends and package level integration create far more technical support data than ever before. All that makes data controls more important than it’s ever been. Now is the time to define, communicate, and implement design data handling rules for all designers and users of FPGAs for defense systems.

Altera (Intel PSG)
San Jose, CA
(408) 544-7000